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| general description the ds2482-100 is an i 2 c-to-1-wire bridge device that interfaces directly to standard (100khz max) or fast (400khz max) i 2 c masters to perform bidirectional pro- tocol conversion between the i 2 c master and any downstream 1-wire slave devices. relative to any attached 1-wire slave device, the ds2482-100 is a 1-wire master. internal, factory-trimmed timers relieve the system host processor from generating time-critical 1-wire waveforms, supporting both standard and over- drive 1-wire communication speeds. to optimize 1-wire waveform generation, the ds2482-100 performs slew-rate control on rising and falling 1-wire edges and provides additional programmable features to match drive characteristics to the 1-wire slave environment. programmable, strong pullup features support 1-wire power delivery to 1-wire devices such as eeproms and sensors. the ds2482-100 combines these features with an output to control an external mosfet for enhanced strong pullup application. the i 2 c slave address assignment is controlled by two binary address inputs, resolving potential conflicts with other i 2 c slave devices in the system. applications features ? i 2 c host interface supports 100khz and 400khz i 2 c communication speeds ? 1-wire master io with selectable active or passive 1-wire pullup ? provides reset/presence, 8-bit, single-bit, and 3-bit 1-wire io sequences ? standard and overdrive 1-wire communication speeds ? slew-controlled 1-wire edges ? strong 1-wire pullup provided by an internal low- impedance signal path ? pctlz output to optionally control an external mosfet for stronger pullup requirements ? two address inputs for i 2 c address assignment ? operating range: 2.9v to 5.5v, -40? to +85? ? 8-pin (150 mils) so and 9-bump wlp packages ds2482-100 single-channel 1-wire master ________________________________________________________________ maxim integrated products 1 19-4930; rev 8; 11/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations appear at end of data sheet. printers medical instruments industrial sensors cell phones, pdas ordering information + denotes a lead(pb)-free/rohs-compliant package. t/t&r = tape and reel. part temp range pin-package ds2482s-100+ -40 c to +85 c 8 so (150 mils) ds2482s-100+t&r -40 c to +85 c 8 so (150 mils) ds2482x-100+t -40 c to +85 c 9 wlp (2.5k pieces) typical operating circuit 1-wire is a registered trademark of maxim integrated products, inc. ds2482-100 sda scl ad1 ad0 pctlz io r p * *r p = i 2 c pullup resistor (see the applications information section for r p sizing). v cc current-limiting resistor refer to application note 4206 optional circuitry 1-wire line c (i 2 c port) 1-wire device 1-wire device 1-wire device
ds2482-100 single-channel 1-wire master 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 2.9v to 5.5v, t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground.........-0.5v to +6v maximum current into any pin.......................................... 20ma operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units 3.3v 2.9 3.3 3.7 supply voltage v cc 5v 4.5 5.0 5.5 v operating current i cc (note 1) 0.75 ma 3.3v 1.9 1-wire input high (notes 2, 3) v ih1 5v 3.4 v 3.3v 0.9 1-wire input low (notes 2, 3) v il1 5v 1.2 v 1-wire weak pullup resistor r wpu (note 4) 1000 1675 1-wire output low v ol1 at 4ma load 0.4 v standard 2.3 2.5 2.7 active pullup on time (notes 4, 5) t apuot overdrive 0.4 0.5 0.6 s v cc 3.2v, 1.5ma load 0.3 strong pullup voltage drop v strpu v cc 5.2v, 3ma load 0.5 v standard (3.3v 10%) 1 4.2 overdrive (3.3v 10%) 5 22.1 standard (5.0v 10%) 2 6.5 pulldown slew rate (note 6) pd src overdrive (5.0v 10%) 10 40 v/s standard (3.3v 10%) 0.8 4 overdrive (3.3v 10%) 2.7 20 standard (5.0v 10%) 1.3 6 pullup slew rate (note 6) pu src overdrive (5.0v 10%) 3.4 31 v/s power-on reset trip point v por 2.2 v 1-wire timing (note 5) (see figures 4, 5, and 6) standard 7.6 8 8.4 write-one/read low time t w1l overdrive 0.9 1 1.1 s standard 13.3 14 15 read sample time t msr overdrive 1.4 1.5 1.8 s standard 65.8 69.3 72.8 1-wire time slot t slot overdrive 9.9 10.5 11.0 s ds2482-100 single-channel 1-wire master _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units standard (3.3v to 0v) 0.54 3.0 overdrive (3.3v to 0v) 0.10 0.59 standard (5.0v to 0v) 0.55 2.2 fall time high-to-low (notes 6, 7) t f1 overdrive (5.0v to 0v) 0.09 0.44 s standard 60 64 68 write-zero low time t w0l overdrive 7.1 7.5 7.9 s standard 5.0 5.3 5.6 write-zero recovery time t rec0 overdrive 2.8 3.0 3.2 s standard 570 600 630 reset low time t rstl overdrive 68.4 72 75.6 s standard 66.5 70 73.5 presence-detect sample time t msp overdrive 7.1 7.5 7.9 s standard 7.6 8 8.4 sampling for short and interrupt t si overdrive 0.7 0.75 0.8 s standard 554.8 584 613.2 reset high time t rsth overdrive 70.3 74 77.7 s control pin (pctlz) output low voltage v olp v cc = 2.9v, 1.2ma load current 0.4 v output high voltage v ohp 0.4ma load current v cc - 0.5v v i 2 c pins (scl, sda, ad0, ad1) (note 8) (see figure 9) v cc = 2.9v to 3.7v -0.5 0.25 v cc low-level input voltage v il v cc = 4.5v to 5.5v -0.5 0.22 v cc v high-level input voltage v ih 0.7 v cc v cc + 0.5v v hysteresis of schmitt trigger inputs v hys 0.05 v cc v low-level output voltage at 3ma sink current v ol 0.4 v output fall time from v ih(min) to v il(max) with a bus capacitance from 10pf to 400pf t of 60 250 ns pulse width of spikes that are suppressed by the input filter t sp sda and scl pins only 50 ns input current each input/output pin with an input voltage between 0.1 x v cc(max) and 0.9 x v cc(max) i i (notes 9, 10) -10 +10 a electrical characteristics (continued) (v cc = 2.9v to 5.5v, t a = -40? to +85?.) ds2482-100 single-channel 1-wire master 4 _______________________________________________________________________________________ note 1: operating current with 1-wire write-byte sequence followed by continuously reading the status register at 400khz in overdrive. note 2: with standard speed, the total capacitive load of the 1-wire bus should not exceed 1nf. otherwise, the passive pullup on threshold v il1 may not be reached in the available time. with overdrive speed, the capacitive load on the 1-wire bus must not exceed 300pf. note 3: active pullup guaranteed to turn on between v il1(max) and v ih1(min) . note 4: active or resistive pullup choice is configurable. note 5: except for t f1 , all 1-wire timing specifications and t apuot are derived from the same timing circuit. therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all these parameters deviate from their typi- cal value in the same direction and by the same degree. note 6: these values apply at full load, i.e., 1nf at standard speed and 0.3nf at overdrive speed. for reduced load, the pulldown slew rate is slightly faster. note 7: fall time high-to-low (t f1 ) is derived from pd src , referenced from 0.9 x v cc to 0.1 x v cc . note 8: all i 2 c timing values are referred to v ih(min) and v il(max) levels. note 9: applies to sda, scl, ad0 and ad1. note 10: the input/output pins of the ds2482-100 do not obstruct the sda and scl lines if v cc is switched off. note 11: the ds2482-100 provides a hold time of at least 300ns for the sda signal (referred to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 12: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 13: a fast-mode i 2 c bus device can be used in a standard-mode i 2 c bus system, but the requirement t su:dat 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c bus specification) before the scl line is released. note 14: c b ?otal capacitance of one bus line in pf. if mixed with high-speed-mode devices, faster fall times according to i 2 c- bus specification version 2.1 are allowed. note 15: i 2 c communication should not take place for the max t oscwup time following a power-on reset. electrical characteristics (continued) (v cc = 2.9v to 5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units input capacitance c i (note 9) 10 pf scl clock frequency f scl 0 400 khz hold time (repeated) start condition (after this period, the first clock pulse is generated.) t hd:sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s setup time for a repeated start condition t su:sta 0.6 s data hold time t hd:dat (notes 11, 12) 0.9 s data setup time t su:dat (note 13) 250 ns setup time for stop condition t su:sto 0.6 s bus free time between a stop and start condition t buf 1.3 s capacitive load for each bus line c b (note 14) 400 pf oscillator warmup time t oscwup (note 15) 100 s ds2482-100 single-channel 1-wire master _______________________________________________________________________________________ 5 pin description pin so wlp name function 1 b3 v cc power-supply input 2 c3 io input/output driver for 1-wire line 3 c2 gnd ground reference 4 b1 scl i 2 c serial clock input. must be connected to v cc through a pullup resistor. 5 b2 sda i 2 c serial data input/output. must be connected to v cc through a pullup resistor. 6 a1 pctlz active-low control output for an external p-channel mosfet. provides extra power to the 1-wire line, e.g., for use with 1-wire devices that require a higher current temporarily to operate. 7 a2 ad1 8 a3 ad0 i 2 c address inputs. must be connected to v cc or gnd. these inputs determine the i 2 c slave address of the device (see figure 8). configuration register i 2 c interface controller input/output controller line xcvr t-time osc ds2482-100 status register read data register sda io pctlz ad0 ad1 scl figure 1. block diagram detailed description the ds2482-100 is a self-timed 1-wire master that sup- ports advanced 1-wire waveform features including standard and overdrive speeds, active pullup, and strong pullup for power delivery. the active pullup affects rising edges on the 1-wire side. the strong pullup function uses the same pullup transistor as the active pullup, but with a different control algorithm. in addition, the strong pullup activates the pctlz pin, controlling optional external circuitry to deliver addition- al power beyond the capabilities of the on-chip pullup transistor. once supplied with command and data, the input/output controller of the ds2482-100 performs time-critical 1-wire communication functions such as reset/presence-detect cycle, read-byte, write-byte, sin- gle-bit r/ w , and triplet for rom search, without requir- ing interaction with the host processor. the host obtains feedback (completion of a 1-wire function, presence pulse, 1-wire short, search direction taken) through the status register and data through the read data register. the ds2482-100 communicates with a host processor through its i 2 c bus interface in standard mode or in fast mode. the logic state of two address pins determines the i 2 c slave address of the ds2482-100, allowing up to four devices operating on the same bus segment without requiring a hub. see figure 1 for a block diagram. ds2482-100 single-channel 1-wire master 6 _______________________________________________________________________________________ v cc 0v 1-wire bus is discharged v il1(max) v ih1(min) t 1 t 2 t apuot t 3 apu = 1 apu = 0 figure 2. rising edge pullup configuration register bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ws spu 1 apu 1ws spu 0 apu device registers the ds2482-100 has three registers that the i 2 c host can read: configuration, status, and read data. these registers are addressed by a read pointer. the position of the read pointer, i.e., the register that the host reads in a subsequent read access, is defined by the instruc- tion the ds2482-100 executed last. to enable certain 1-wire features, the host has read and write access to the configuration register. configuration register the ds2482-100 supports three 1-wire features that are enabled or selected through the configuration register. these features are: active pullup (apu) strong pullup (spu) 1-wire speed (1ws) these features can be selected in any combination. while apu and 1ws maintain their state, spu returns to its inactive state as soon as the strong pullup has ended. after a device reset (power-up cycle or initiated by the device reset command), the configuration register reads 00h. when writing to the configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one? complement of the lower nibble (bits 3 to 0). when read, the upper nibble is always 0h. active pullup (apu) the apu bit controls whether an active pullup (con- trolled slew-rate transistor) or a passive pullup (r wpu resistor) is used to drive a 1-wire line from low to high. when apu = 0, active pullup is disabled (resistor mode). active pullup should always be selected unless there is only a single slave on the 1-wire line. the active pullup does not apply to the rising edge of a presence pulse or a recovery after a short on the 1-wire line. the circuit that controls rising edges (figure 2) oper- ates as follows: at t 1 , the pulldown (from ds2482-100 or 1-wire slave) ends. from this point on, the 1-wire bus is pulled high through r wpu internal to the ds2482-100. v cc and the capacitive load of the 1-wire line determine the slope. in case that active pullup is disabled (apu = 0), the resistive pullup continues, as represented by the solid line. with active pullup enabled (apu = 1), and when at t 2 the voltage has reached a level between v il1(max) and v ih1(min) , the ds2482-100 actively pulls the 1-wire line high, applying a controlled slew rate as represented by the dashed line. the active pullup continues until t apuot is expired at t 3 . from that time on the resistive pullup continues. see the strong pullup (spu) section for a way to keep the pullup transistor conducting beyond t 3 . ds2482-100 strong pullup (spu) the spu bit is used to activate the strong pullup func- tion prior to a 1-wire write byte or 1-wire single bit command. strong pullup is commonly used with 1-wire eeprom devices when copying scratchpad data to the main memory or when performing an sha-1 computa- tion and with parasitically powered temperature sen- sors or a/d converters. the respective device data sheets specify the location in the communications pro- tocol after which the strong pullup should be applied. the spu bit must be set immediately prior to issuing the command that puts the 1-wire device into the state where it needs the extra power. the strong pullup uses the same internal pullup transistor as the active pullup feature. for cases where the internal strong pullup has insufficient strength, the pctlz pin can be used to con- trol an external p-channel mosfet to supply additional power beyond the drive capability of the ds2482-100 to the 1-wire line. see the v strpu parameter in the electrical characteristics to determine if the internal strong pullup is sufficient given the current load on the device. if spu is 1, the ds2482-100 treats the rising edge of the time slot in which the strong pullup starts as if the active pullup was activated. however, in contrast to the active pullup, the strong pullup, i.e., the internal pullup transis- tor, remains conducting, as shown in figure 3, until one of three events occurs: the ds2482-100 receives a command that generates 1-wire communication (the typical case); the spu bit in the configuration register is written to 0; or the ds2482-100 receives the device reset command. as long as the strong pullup is active, the pctlz output is low. when the strong pullup ends, the spu bit is automatically reset to 0. using the strong pullup feature does not change the state of the apu bit in the configuration register. 1-wire speed (1ws) the 1ws bit determines the timing of any 1-wire com- munication generated by the ds2482-100. all 1-wire slave devices support standard speed (1ws = 0), where the transfer of a single bit (t slot in figure 3) is completed within 65?. many 1-wire devices can also communicate at a higher data rate, called overdrive speed. to change from standard to overdrive speed, a 1-wire device needs to receive an overdrive-skip rom or overdrive-match rom command, as explained in the 1-wire device data sheets. the change in speed occurs immediately after the 1-wire device has received the speed-changing command code. the ds2482-100 must take part in this speed change to stay synchronized. this is accomplished by writing to the configuration register with the 1ws bit as 1 imme- diately after the 1-wire byte command that changes the speed of a 1-wire device. writing to the configuration register with the 1ws bit as 0, followed by a 1-wire reset command, changes the ds2482-100 and any 1-wire devices on the active 1-wire line back to stan- dard speed. ds2482-100 resistive pullup ds2482-100 pulldown ds2482-100 strong pullup v cc 0v pctlz write-zero case write-one case t slot last bit of 1-wire write byte or 1-wire single bit function next time slot or 1-wire reset figure 3. low-impedance pullup timing single-channel 1-wire master _______________________________________________________________________________________ 7 ds2482-100 single-channel 1-wire master 8 _______________________________________________________________________________________ status register the read-only status register is the general means for the ds2482-100 to report bit-type data from the 1-wire side, 1-wire busy status, and its own reset status to the host processor. all 1-wire communication commands and the device reset command position the read pointer at the status register for the host processor to read with minimal protocol overhead. status information is updated during the execution of certain commands only. details are given in the description of the various status bits that follow. 1-wire busy (1wb) the 1wb bit reports to the host processor whether the 1-wire line is busy. during 1-wire communication 1wb is 1; once the command is completed, 1wb returns to its default 0. details on when 1wb changes state and for how long it remains at 1 are found in the function commands section. presence-pulse detect (ppd) the ppd bit is updated with every 1-wire reset com- mand. if the ds2482-100 detects a presence pulse from a 1-wire device at t msp during the presence-detect cycle, the ppd bit is set to 1. this bit returns to its default 0 if there is no presence pulse or if the 1-wire line is shorted during a subsequent 1-wire reset command. short detected (sd) the sd bit is updated with every 1-wire reset com- mand. if the ds2482-100 detects a logic 0 on the 1-wire line at t si during the presence-detect cycle, the sd bit is set to 1. this bit returns to its default 0 with a subsequent 1-wire reset command provided that the short has been removed. if sd is 1, ppd is 0. the ds2482-100 cannot distinguish between a short and a ds1994 or ds2404 signaling a 1-wire interrupt. for this reason, if a ds2404 or ds1994 is used in the applica- tion, the interrupt function must be disabled. the inter- rupt signaling is explained in the respective 1-wire device data sheets. logic level (ll) the ll bit reports the logic state of the active 1-wire line without initiating any 1-wire communication. the 1-wire line is sampled for this purpose every time the status register is read. the sampling and updating of the ll bit takes place when the host processor has addressed the ds2482-100 in read mode (during the acknowledge cycle), provided that the read pointer is positioned at the status register. device reset (rst) if the rst bit is 1, the ds2482-100 has performed an internal reset cycle, either caused by a power-on reset or from executing the device reset command. the rst bit is cleared automatically when the ds2482-100 exe- cutes a write configuration command to restore the selection of the desired 1-wire features. single bit result (sbr) the sbr bit reports the logic state of the active 1-wire line sampled at t msr of a 1-wire single bit command or the first bit of a 1-wire triplet command. the power-on default of sbr is 0. if the 1-wire single bit command sends a 0 bit, sbr should be 0. with a 1-wire triplet command, sbr could be 0 as well as 1, depending on the response of the 1-wire devices connected. the same result applies to a 1-wire single bit command that sends a 1 bit. triplet second bit (tsb) the tsb bit reports the logic state of the active 1-wire line sampled at t msr of the second bit of a 1-wire triplet command. the power-on default of tsb is 0. this bit is updated only with a 1-wire triplet command and has no function with other commands. branch direction taken (dir) whenever a 1-wire triplet command is executed, this bit reports to the host processor the search direction that was chosen by the third bit of the triplet. the power-on default of dir is 0. this bit is updated only with a 1-wire triplet command and has no function with other commands. for additional information, see the description of the 1-wire triplet command and application note 187: 1-wire search algorithm . status register bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir tsb sbr rst ll sd ppd 1wb ds2482-100 single-channel 1-wire master _______________________________________________________________________________________ 9 function commands the ds2482-100 understands eight function com- mands that fall into four categories: device control, i 2 c communication, 1-wire setup, and 1-wire communica- tion. the feedback path to the host is controlled by a read pointer, which is set automatically by each func- tion command for the host to efficiently access relevant information. the host processor sends these com- mands and applicable parameters as strings of one or two bytes using the i 2 c interface. the i 2 c protocol requires that each byte be acknowledged by the receiving party to confirm acceptance or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the communication. see the i 2 c interface section for details of the i 2 c protocol including acknowledge. the function commands are as follows: 1) device reset 5) 1-wire single bit 2) set read pointer 6) 1-wire write byte 3) write configuration 7) 1-wire read byte 4) 1-wire reset 8) 1-wire triplet table 1. valid pointer codes device reset command code f0h command parameter none description performs a global reset of device state machine logic. terminates any ongoing 1-wire communication. typical use device initialization after power-up; reinitialization (reset) as desired. restriction none (can be executed at any time). error response none command duration maximum 525ns. counted from falling scl edge of the command code acknowledge bit. 1-wire activity ends maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling). status bits affected rst set to 1; 1wb, ppd, sd, sbr, tsb, dir set to 0. configuration bits affected 1ws, apu, spu set to 0. set read pointer command code e1h command parameter pointer code (see table 1) description sets the read pointer to the specified register. overwrites the read pointer position of any 1-wire communication command in progress. typical use to prepare reading the result from a 1-wire read byte command; random read access of registers. restriction none (can be executed at any time). error response if the pointer code is not valid, the pointer code is not acknowledged and the command is ignored. command duration none. the read pointer is updated on the rising scl edge of the pointer code acknowledge bit. 1-wire activity not affected. read pointer position as specified by the pointer code. status bits affected none configuration bits affected none register selection code status register f0h read data register e1h configuration register c3h ds2482-100 single-channel 1-wire master 10 ______________________________________________________________________________________ write configuration command code d2h command parameter configuration byte description writes a new configuration byte. the new settings take effect immediately. note: when writing to the configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the ones complement of the lower nibble (bits 3 to 0). when read, the upper nibble is always 0h. typical use defining the features for subsequent 1-wire communication. restriction 1-wire activity must have ended before the ds2482-100 can process this command. error response command code and parameter are not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration none. the configuration register is updated on the rising scl edge of the configuration-byte acknowledge bit. 1-wire activity none read pointer position configuration register (to verify write). status bits affected rst set to 0. configuration bits affected 1ws, spu, apu updated. 1-wire reset command code b4h command parameter none description generates a 1-wire reset/presence-detect cycle (figure 4) at the 1-wire line. the state of the 1-wire line is sampled at t si and t msp and the result is reported to the host processor through the status register, bits ppd and sd. typical use to initiate or end any 1-wire communication sequence. restriction 1-wire activity must have ended before the ds2482-100 can process this command. error response command code is not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration t rstl + t rsth + maximum 262.5ns, counted from the falling scl edge of the command code acknowledge bit. 1-wire activity begins maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling). status bits affected 1wb (set to 1 for t rstl + t rsth ), ppd is updated at t rstl + t msp , sd is updated at t rstl + t si . configuration bits affected 1ws and apu apply. ds2482-100 single-channel 1-wire master ______________________________________________________________________________________ 11 pullup ds2482-100 pulldown 1-wire slave pulldown v cc v ih1 v il1 0v reset pulse resistive pullup presence pulse apu controlled edge presence/short detect t rstl t si t msp t rsth t f1 figure 4. 1-wire reset/presence-detect cycle 1-wire single bit command code 87h command parameter bit byte description generates a single 1-wire time slot with a bit value v as specified by the bit byte at the 1-wire line (see table 2). a v value of 0b generates a write-zero time slot (figure 5); a v value of 1b generates a write-one time slot, which also functions as a read-data time slot (figure 6). in either case, the logic level at the 1-wire line is tested at t msr and sbr is updated. typical use to perform single-bit writes or reads at the 1-wire line when single bit communication is necessary (the exception). restriction 1-wire activity must have ended before the ds2482-100 can process this command. error response command code and bit byte are not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration t slot + maximum 262.5ns, counted from the falling scl edge of the first bit (msb) of the bit byte. 1-wire activity begins maximum 262.5ns after the falling scl edge of the msb of the bit byte. read pointer position status register (for busy polling and data reading). status bits affected 1wb (set to 1 for t slot ), sbr is updated at t msr , dir (may change its state). configuration bits affected 1ws, apu, spu apply. table 2. bit allocation in the bit byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v x x x x x x x x = don? care. ds2482-100 single-channel 1-wire master 12 ______________________________________________________________________________________ pullup (see figure 2) ds2482-100 pulldown v cc v ih1 v il1 0v t slot t rec0 t wol t msr t f1 figure 5. write-zero time slot pullup (see figure 2) ds2482-100 pulldown 1-wire slave pulldown v cc v ih1 v il1 0v t slot t w1l t msr t f1 note: depending on its internal state, a 1-wire slave device transmits data to its master (e.g. the ds2482-100). when responding wit h a 0, a 1-wire slave starts pulling the line low during t w1l . its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, a 1-wire slave does not hold the line low at all, and the voltage starts rising as soon as t w1l is over. 1-wire device data sheets use the term t rl instead of t w1l to describe a read-data time slot. technically, t rl and t w1l have identical specifications and cannot be distinguished from each other. figure 6. write-one and read-data time slot ds2482-100 single-channel 1-wire master ______________________________________________________________________________________ 13 1-wire write byte command code a5h command parameter data byte description writes a single data byte to the 1-wire line. typical use to write commands or data to the 1-wire line. equivalent to executing eight 1-wire single bit commands, but faster due to less i 2 c traffic. restriction 1-wire activity must have ended before the ds2482-100 can process this command. error response command code and data byte are not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration 8 x t slot + maximum 262.5ns, counted from falling edge of the last bit (lsb) of the data byte. 1-wire activity begins maximum 262.5ns after falling scl edge of the lsb of the data byte (i.e., before the data byte acknowledge). note: the bit order on the i 2 c bus and the 1-wire line is different (1-wire: lsb first; i 2 c: msb first). therefore, 1-wire activity cannot begin before the ds2482-100 has received the full data byte. read pointer position status register (for busy polling). status bits affected 1wb (set to 1 for 8 x t slot ). configuration bits affected 1ws, spu, apu apply. 1-wire read byte command code 96h command parameter none description generates eight read-data time slots on the 1-wire line and stores result in the read data register. typical use to read data from the 1-wire line. equivalent to executing eight 1-wire single bit commands with v = 1 (write-one time slot), but faster due to less i 2 c traffic. restriction 1-wire activity must have ended before the ds2482-100 can process this command. error response command code is not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration 8 x t slot + maximum 262.5ns, counted from the falling scl edge of the command code acknowledge bit. 1-wire activity begins maximum 262.5ns after the falling scl edge of the command code acknowledge bit. read pointer position status register (for busy polling). note: to read the data byte received from the 1-wire line, issue the set read pointer command and select the read data register. then access the ds2482-100 in read mode. status bits affected 1wb (set to 1 for 8 x t slot ). configuration bits affected 1ws, apu apply. ds2482-100 single-channel 1-wire master 14 ______________________________________________________________________________________ 1-wire triplet command code 78h command parameter direction byte description generates three time slots: two read time slots and one write time slot at the 1-wire line. the type of write time slot depends on the result of the read time slots and the direction byte. the direction byte determines the type of write time slot if both read time slots are 0 (a typical case). in this case, the ds2482-100 generates a write-one time slot if v = 1 and a write-zero time slot if v = 0. see table 3. if the read time slots are 0 and 1, they are followed by a write-zero time slot. if the read time slots are 1 and 0, they are followed by a write-one time slot. if the read time slots are both 1 (error case), the subsequent write time slot is a write-one. typical use to perform a 1-wire search rom sequence; a full sequence requires this command to be executed 64 times to identify and address one device. restriction 1-wire activity must have ended before the ds2482-100 can process this command. error response command code and direction byte is not acknowledged if 1wb = 1 at the time the command code is received and the command is ignored. command duration 3 x t slot + maximum 262.5ns, counted from the falling scl edge of the first bit (msb) of the direction byte. 1-wire activity begins maximum 262.5ns after the falling scl edge of the msb of the direction byte. read pointer position status register (for busy polling). status bits affected 1wb (set to 1 for 3 x t slot ), sbr is updated at the first t msr , tsb and dir are updated at the second t msr (i.e., at t slot + t msr ). configuration bits affected 1ws, apu apply. table 3. bit allocation in the direction byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v x x x x x x x x = don? care. ds2482-100 single-channel 1-wire master ______________________________________________________________________________________ 15 i 2 c interface general characteristics the i 2 c bus uses a data line (sda) plus a clock signal (scl) for communication. both sda and scl are bidi- rectional lines, connected to a positive supply voltage through a pullup resistor. when there is no communica- tion, both lines are high. the output stages of devices connected to the bus must have an open drain or open collector to perform the wired-and function. data on the i 2 c bus can be transferred at rates of up to 100kbps in standard mode and up to 400kbps in fast mode. the ds2482-100 works in both modes. a device that sends data on the bus is defined as a transmitter, and a device receiving data is defined as a receiver. the device that controls the communication is called a master. the devices that are controlled by the master are slaves. to be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. data transfers can be initiated only when the bus is not busy. the master generates the serial clock (scl), con- trols the bus access, generates the start and stop conditions, and determines the number of data bytes transferred between start and stop (figure 7). data is transferred in bytes with the most significant bit being transmitted first. after each byte follows an acknowledge bit to allow synchronization between master and slave. slave address the slave address to which the ds2482-100 responds is shown in figure 8. the logic state at the address pins ad0 and ad1 determines the value of the address bits a0 and a1. the address pins allow the device to respond to one of four possible slave addresses. the slave address is part of the slave address/control byte. the last bit of the slave address/control byte (r/ w ) defines the data direction. when set to 0, subsequent data flows from master to slave (write access); when set to 1, data flows from slave to master (read access). sda scl idle 1?7 8 9 1?7 8 9 1?7 8 9 start condition stop condition repeated start slave address r/w ack ack data ack/ nack data msb first msb lsb msb lsb repeated if more bytes are transferred figure 7. i 2 c protocol overview figure 8. ds2482-100 slave address 0 a6 msb 0 a5 1 a4 1 a3 7-bit slave address 0 a2 ad1 a1 ad0 a0 r/w determines read or write ad1, ad0 pin states ds2482-100 single-channel 1-wire master 16 ______________________________________________________________________________________ i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. the timing references are defined in figure 9. bus idle or not busy: both sda and scl are inac- tive and in their logic-high states. start condition: to initiate communication with a slave, the master must generate a start condition. a start condition is defined as a change in state of sda from high to low while scl remains high. stop condition: to end communication with a slave, the master must generate a stop condition. a stop condition is defined as a change in state of sda from low to high while scl remains high. repeated start condition: repeated starts are commonly used for read accesses to select a spe- cific data source or address to read from. the mas- ter can use a repeated start condition at the end of a data transfer to immediately initiate a new data transfer following the current one. a repeated start condition is generated the same way as a normal start condition, but without leaving the bus idle after a stop condition. data valid: with the exception of the start and stop condition, transitions of sda can occur only during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl; see figure 9). there is one clock pulse per bit of data. data is shifted into the receiving device during the rising edge of scl. when finished with writing, the master must release the sda line for a sufficient amount of setup time (minimum t su:dat + t r in figure 9) before the next rising edge of scl to start reading. the slave shifts out each data bit on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. the master generates all scl clock pulses, including those needed to read from a slave. acknowledge: typically a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. the master must gen- erate a clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull sda low during the acknowledge clock pulse in such a way that sda is stable low during the high period of the acknowledge-related clock pulse plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl). not acknowledged by slave: a slave device may be unable to receive or transmit data, for example, because it is busy performing some real-time func- tion. in this case, the slave device does not acknowl- edge its slave address and leaves the sda line high. a slave device that is ready to communicate acknowledges at least its slave address. however, scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start spike suppression t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 9. i 2 c timing diagram ds2482-100 single-channel 1-wire master ______________________________________________________________________________________ 17 some time later the slave may refuse to accept data, possibly because of an invalid command code or parameter. in this case, the slave device does not acknowledge any of the bytes that it refuses and leaves sda high. in either case, after a slave has failed to acknowledge, the master first should gener- ate a repeated start condition or a stop condition followed by a start condition to begin a new data transfer. not acknowledged by master: at some time when receiving data, the master must signal an end of data to the slave device. to achieve this, the master does not acknowledge the last byte that it has received from the slave. in response, the slave releases sda, allowing the master to generate the stop condition. writing to the ds2482-100 to write to the ds2482-100, the master must access the device in write mode, i.e., the slave address must be sent with the direction bit set to 0. the next byte to be sent is a command code, which, depending on the command, may be followed by a command parameter. the ds2482-100 acknowledges valid command codes and expected/valid command parameters. additional bytes or invalid command parameters are never acknowledged. reading from the ds2482-100 to read from the ds2482-100, the master must access the device in read mode, i.e., the slave address must be sent with the direction bit set to 1. the read pointer determines the register that the master reads from. the master can continue reading the same register over and over again, without having to readdress the device, e.g., to watch the 1wb changing from 1 to 0. to read from a different register, the master must issue the set read pointer command and then access the ds2482- 100 again in read mode. i 2 c communication examples see tables 4 and 5 for the i 2 c communication legend and data direction codes. table 4. i 2 c communication?egend symbol description s start condition ad, 0 select ds2482-100 for write access ad, 1 select ds2482-100 for read access sr repeated start condition p stop condition a acknowledged a\ not acknowledged (idle) bus not busy ds2482-100 single-channel 1-wire master 18 ______________________________________________________________________________________ device reset (after power-up) activities that are underlined denote an optional read access to verify the success of the command. set read pointer (to read from another register) case a: valid read pointer code c3h is the valid read pointer code for the configuration register. case b: invalid read pointer code e5h is an invalid read pointer code. write configuration (before starting 1-wire activity) case a: 1-wire idle (1wb = 0) activities that are underlined denote an optional read access to verify the success of the command. case b: 1-wire busy (1wb = 1) the master should stop and restart as soon as the ds2482-100 does not acknowledge the command code. 1-wire reset (to begin or end 1-wire communication) case a: 1-wire idle (1wb = 0), no busy polling to read the result in the first cycle, the master sends the command. then the master waits (idle) for the 1-wire reset to complete. in the second cycle, the ds2482-100 is accessed to read the result of the 1-wire reset from the status register. case b: 1-wire idle (1wb = 0), busy polling until the 1-wire command is completed, then read the result case c: 1-wire busy (1wb = 1) the master should stop and restart as soon as the ds2482-100 does not acknowledge the command code. s ad,0 a 1wrs a\ p s ad,0 a 1wrs a ds2482-100 single-channel 1-wire master ______________________________________________________________________________________ 19 1-wire single bit (to generate a single time slot on the 1-wire line) case a: 1-wire idle (1wb = 0), no busy polling the idle time is needed for the 1-wire function to complete. then access the device in read mode to get the result from the 1-wire single bit command. case b: 1-wire idle (1wb = 0), busy polling until the 1-wire command is completed when 1wb has changed from 1 to 0, the status register holds the valid result of the 1-wire single bit command. case c: 1-wire busy (1wb = 1) the master should stop and restart as soon as the ds2482-100 does not acknowledge the command code. 1-wire write byte (to send a command code to the 1-wire line) case a: 1-wire idle (1wb = 0), no busy polling 33h is the valid 1-wire rom function command for read rom. the idle time is needed for the 1-wire function to complete. there is no data read back from the 1-wire line with this command. case b: 1-wire idle (1wb = 0), busy polling until the 1-wire command is completed. when 1wb has changed from 1 to 0, the 1-wire write byte command is completed. case c: 1-wire busy (1wb = 1) the master should stop and restart as soon as the ds2482-100 does not acknowledge the command code. s ad,0 a 1wwb a\ p s ad,0 a 1wwb a 33h a ad,1 sr aa ds2482-100 single-channel 1-wire master 20 ______________________________________________________________________________________ 1-wire read byte (to read a byte from the 1-wire line) case a: 1-wire idle (1wb = 0), no busy polling, set read pointer after idle time the idle time is needed for the 1-wire function to complete. then set the read pointer to the read data register (code e1h) and access the device again to read the data byte that was obtained from the 1-wire line. case b: 1-wire idle (1wb = 0), no busy polling, set read pointer before idle time the read pointer is set to the read data register (code e1h) while the 1-wire read byte command is still in progress. then, after the 1-wire function is completed, the device is accessed to read the data byte that was obtained from the 1-wire line. case c: 1-wire idle (1wb = 0), busy polling until the 1-wire command is completed poll the status register until the 1wb bit has changed from 1 to 0. then set the read pointer to the read data register (code e1h) and access the device again to read the data byte that was obtained from the 1-wire line. case d: 1-wire busy (1wb = 1) the master should stop and restart as soon as the ds2482-100 does not acknowledge the command code. s ad,0 a 1wrb a\ p s ad,0 a 1wrb ad,0 a srp a a e1h a sr ad,1 a ds2482-100 single-channel 1-wire master ______________________________________________________________________________________ 21 applications information sda and scl pullup resistors sda is an open-drain output on the ds2482-100 that requires a pullup resistor to realize high-logic levels. because the ds2482-100 uses scl only as input (no clock stretching), the master can drive scl either through an open-drain/-collector output with a pullup resistor or a push-pull output. pullup resistor r p sizing according to the i 2 c specification, a slave device must be able to sink at least 3ma at a v ol of 0.4v. this dc condition determines the minimum value of the pullup resistor as: r p(min) = (v cc - 0.4v)/3ma with an operating voltage of 5.5v, the minimum value for the pullup resistor is 1.7k . the ?inimum r p ?line in figure 11 shows how the minimum pullup resistor changes with the operating voltage. for i 2 c systems, the rise time and fall time are mea- sured from 30% to 70% of the pullup voltage. the maxi- mum bus capacitance, c b , is 400pf. the maximum rise time must not exceed 1000ns at standard speed and 300ns at fast speed. assuming maximum rise time, the maximum resistor value at any given capacitance c b is calculated as: r pmaxs = 1000ns/[c b x ln(7/3)] (standard speed) r pmaxf = 300ns/[c b x ln(7/3)] (fast speed) for a bus capacitance of 400pf, the maximum pullup resistor values are 2.95k at standard speed and 885 at fast speed. a value between 1.7k and 2.95k meets all requirements at standard speed. because an 885 pullup resistor, as would be required to meet the rise time specification at fast speed and 400pf bus capacitance, is lower than r p(min) at 5.5v, a different approach is necessary. the ?ax load at min r p fast mode?line in figure 11 is generated by first calculating the minimum pullup resistor at any given operating voltage (?inimum r p ?line) and then calculating the respective bus capacitance that yields a 300ns rise time. only for pullup voltages of 3v and lower can the maximum permissible bus capacitance of 400pf be maintained. a 1-wire triplet (to perform a search rom function on the 1-wire line) case a: 1-wire idle (1wb = 0), no busy polling the idle time is needed for the 1-wire function to complete. then access the device in read mode to get the result from the 1-wire triplet command. case b: 1-wire idle (1wb = 0), busy polling until the 1-wire command is completed when 1wb has changed from 1 to 0, the status register holds the valid result of the 1-wire triplet command. case c: 1-wire busy (1wb = 1) the master should stop and restart as soon as the ds2482-100 does not acknowledge the command code. s ad,0 a 1wt a\ p s ad,0 a 1wt a ds2482-100 single-channel 1-wire master 22 ______________________________________________________________________________________ ds2482-100 sda scl ad1 ad0 pctlz io r p * *r p = i 2 c pullup resistor (see the applications information section for r p sizing). v cc v cc v cc current-limiting resistor refer to application note 4206 1-wire line 1-wire line 1-wire device #1 (with special power requirements) 1-wire device #2 ds2482-100 sda scl ad0 ad1 pctlz io c (i 2 c port) figure 10. application schematic minimum r p max load at min r p fast mode 2000 minimum r p ( ) load (pf) pullup voltage (v) 1600 1200 800 400 12345 0 500 400 300 200 100 0 figure 11. i 2 c fast mode pullup resistor selection chart reduced bus capacitance of 300pf is acceptable for pullup voltages of 4v and lower. for fast speed operation at any pullup voltage, the bus capacitance must not exceed 200pf. the corresponding pullup resistor value at the voltage is indicated by the ?inimum r p ?line. ds2482-100 single-channel 1-wire master ______________________________________________________________________________________ 23 pctlz sda scl 1 2 8 7 ad0 ad1 io gnd v cc so (150 mils) top view 3 4 6 5 ds2482-100 wlp top view (bump side down) 123 b c a pctlz ad1 ad0 scl sda v cc gnd io + ds2482-100 ds2482-100 wlp 123 b c a + top mark 24821 yywwrr ###xx + pin configurations package type package code document no. 8 so (150 mils) s8+4 21-0041 9 wlp w92a1+1 21-0067 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . ds2482-100 single-channel 1-wire master maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed updated the features bullets. 1 updated the v il1 and r wpu values in the electrical characteristics table. 2 minor corrections to figure 1; updated the detailed description section to clarify information about the active pullup and strong pullup. 5 replaced the strong pullup (spu) section description and replaced figure 4. 7 5 061208 removed timing inaccuracies in figure 8. 14 created newer template-style data s heet. all 6 7/08 replaced figure 8. 16 7 8/08 deleted the 1-wire line termination resistor and references to it in the typical operating circu it and in figure 11. 1, 23 8 11/09 ? corrected the recommendation for using active pullup (apu). ? removed the references to presence-pulse masking. 1C7, 9C12, 15, 16, 21, 22, 24 |
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